tool: VHDL Object Model (VOM)

---

Language:	VHDL
Version:	1.0
Parts:	parser
Author:	David Benz <dbenz@thor.ece.uc.edu> and Phillip Baraona <pbaraona@thor.ece.uc.edu>
Location:	ftp://thor.ece.uc.edu/pub/vhdl/tools/vhdl-object-model.tar.gz
Description:	VOM 1.0 is an object-oriented syntactic specification for VHDL written using the REFINE software design and synthesis environment. In simpler terms, it is a VHDL parser which builds an object tree from VHDL source code. If you are interested in transforming VHDL into some other form (source code, whatever) you might be interested in this. The parse tree (in the form of an object tree) is provided, you would just need to add your own transformations. VOM isn't complete. The semantic information is not included (type checking, certain syntactic-rules, etc.). VOM 1.0 should parse most VHDL programs. However, it will not detect errors such as a wait statement in a process statement with an explicit sensitivity list.
Updated:	November 1st, 1994

language: VHDL

category: electrical engineering languages summary, or expanded.