language: VHDL

`Language:`	VHDL
`Package:`	ALLIANCE
`Version:`	1.1
`Parts:`	compiler, simulator, tools and environment, documentation
`Author:`	?
`Location:`	ftp://ftp.ibp.fr/ibp/softs/masi/alliance/
`Description:`	ALLIANCE 1.1 is a complete set of CAD tools for teaching Digital CMOS VLSI Design in Universities. It includes VHDL compiler and simulator, logic synthesis tools, automatic place and route, etc... ALLIANCE is the result of a ten years effort at University Pierre et Marie Curie (PARIS VI, France).
`Ports:`	Sun4, also not well supported: Mips/Ultrix, 386/SystemV
`Discussion:`	alliance-request@masi.ibp.fr
`Contact:`	cao-vlsi@masi.ibp.fr
`Updated:`	Febuary 16th, 1993

`Language:`	VHDL
`Package:`	VHDL Object Model (VOM)
`Version:`	1.0
`Parts:`	parser
`Author:`	David Benz <dbenz@thor.ece.uc.edu> and Phillip Baraona <pbaraona@thor.ece.uc.edu>
`Location:`	ftp://thor.ece.uc.edu/pub/vhdl/tools/vhdl-object-model.tar.gz
`Description:`	VOM 1.0 is an object-oriented syntactic specification for VHDL written using the REFINE software design and synthesis environment. In simpler terms, it is a VHDL parser which builds an object tree from VHDL source code. If you are interested in transforming VHDL into some other form (source code, whatever) you might be interested in this. The parse tree (in the form of an object tree) is provided, you would just need to add your own transformations. VOM isn't complete. The semantic information is not included (type checking, certain syntactic-rules, etc.). VOM 1.0 should parse most VHDL programs. However, it will not detect errors such as a wait statement in a process statement with an explicit sensitivity list.
`Updated:`	November 1st, 1994

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