| These are languages used for simulating, designing, and specifying circuits. |
| VHDL | |
| ALLIANCE | |
| 1.1 | |
| compiler, simulator, tools and environment, documentation | |
| ? | |
| ftp://ftp.ibp.fr/ibp/softs/masi/alliance/ | |
| ALLIANCE 1.1 is a complete set of CAD tools for teaching Digital CMOS VLSI Design in Universities. It includes VHDL compiler and simulator, logic synthesis tools, automatic place and route, etc... ALLIANCE is the result of a ten years effort at University Pierre et Marie Curie (PARIS VI, France). | |
| Sun4, also not well supported: Mips/Ultrix, 386/SystemV | |
| alliance-request@masi.ibp.fr | |
| cao-vlsi@masi.ibp.fr | |
| Febuary 16th, 1993 |
| EDIF (Electronic Design Interchange Format) | |
| Berkeley EDIF200 | |
| 7.6 | |
| translator-building toolkit | |
| Wendell C. Baker and Prof A. Richard Newton of the Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, CA | |
| ?? ftp://ic.berkeley.edu/pub/edif ?? | |
| ? | |
| no-profit w/o permission | |
| ? | |
| 1990/07 |
| CASE-DSP (Computer Aided Software Eng. for Digital Signal Proc) | |
| Ptolemy | |
| 0.6 | |
| grahpical algorithm layout, code generator, simulator | |
| ? | |
| ftp://ptolemy.eecs.berkeley.edu/pub/ptolemy/ptolemy0.6/ | |
|
Ptolemy provides a highly flexible foundation for the
specification, simulation, and rapid prototyping of systems.
It is an object oriented framework within which diverse models
of computation can co-exist and interact. For example, using
Ptolemy a data-flow system can be easily connected to a
hardware simulator which in turn may be connected to a
discrete-event system, etc. Because of this, Ptolemy can be
used to model entire systems.
In addition, Ptolemy now has code generation capabilities. from a flow graph description, Ptolemy can generate both C code and DSP assembly code for rapid prototyping. Note that code generation is not yet complete, and is included in the current release for demonstration purposes only. | |
| C++, C | |
| Sun-4, MIPS/Ultrix; DSP56001, DSP96002. FreeBSD | |
| active research project | |
| ptolemy-hackers-request@ohm.berkeley.edu | |
| ptolemy@ohm.berkeley.edu | |
| May 28th, 1996 |
| SAOL, SASL (the MPEG-4 Structured Audio Orchestra Language and Structured Audio Score Language) | |
| saolc | |
| 0.5 | |
| parser, interpreter, grammar, core opcode implementation | |
| Eric Scheirer, MIT Media Laboratory | |
| http://sound.media.mit.edu/~eds/mpeg4 | |
|
SAOL is an audio processing and digital synthesis and effects
language. It is part of the MPEG-4 standard, and allows the
flexible description of synthesizers and effects-processing
algorithms within than toolset.
SAOL is historically related to Csound and other "Music N" languages, but is more flexible and easy to use than these. While maintaining features such as the instrument/score distinction and dual-rate processing, it adds user-defined opcodes, more well-defined rate semantics, more lexical flexibility, and an improved syntax. | |
| forthcoming | |
| This implementation is being developed as the official Reference Software for the Structured Audio component of ISO 14496 (MPEG-4). | |
| |
| many known and being worked on. | |
| source code is released to the public domain | |
| C compiler only; lex/yacc to rebuild parser not much fun without audio capability | |
| At least SGI, Alpha, NT, Win95, Linux, and SunOS systems | |
| Word length and byte-order independent | |
| Under active development | |
| saol-dev-request@media.mit.edu to be added to the SAOL developers' mailing list | |
| Eric Scheirer <eds@media.mit.edu> | |
| Eric Scheirer <eds@media.mit.edu> | |
| http://sound.media.mit.edu/~eds/mpeg4 and the mailing list | |
| Eric Scheirer <eds@media.mit.edu> | |
| 07/1997 |
| SPAM Compiler | |
| SPAM | |
| ? | |
| ? | |
| ? | |
| http://www.ee.princeton.edu/spam | |
| The SPAM Compiler is a retargetable optimizing compiler for embedded fixed- point DSP processors. SPAM is built on top of the SUIF Compiler, which serves as the "front and middle"-end. The back-end of the SPAM Compiler consists of two components. The first component is a set of data structures that store the various representations of the source program (e.g. calling graph, control-flow graphs, expression DAGs). The second component is a suite of retargetable algorithms that perform code generation and machine-dependent code optimization. | |
| ? |
| Pascal, Lisp, APL, Scheme, SASL, CLU, Smalltalk, Prolog | |
| Tim Budd's C++ implementation of Kamin's interpreters | |
| ? | |
| interpretors, documentation | |
| Tim Budd <budd@cs.orst.edu> | |
| ? ftp://cs.orst.edu/pub/budd/kamin/*.shar | |
| a set of interpretors written as subclasses based on "Programming Languages, An Interpreter-Based Approach", by Samuel Kamin. | |
| C++ | |
| ? | |
| Tim Budd <budd@fog.cs.orst.edu> | |
| September 12th, 1991 |
| VHDL | |
| VHDL Object Model (VOM) | |
| 1.0 | |
| parser | |
| David Benz <dbenz@thor.ece.uc.edu> and Phillip Baraona <pbaraona@thor.ece.uc.edu> | |
| ftp://thor.ece.uc.edu/pub/vhdl/tools/vhdl-object-model.tar.gz | |
|
VOM 1.0 is an object-oriented syntactic specification for VHDL
written using the REFINE software design and synthesis
environment. In simpler terms, it is a VHDL parser which builds
an object tree from VHDL source code.
If you are interested in transforming VHDL into some other form (source code, whatever) you might be interested in this. The parse tree (in the form of an object tree) is provided, you would just need to add your own transformations. VOM isn't complete. The semantic information is not included (type checking, certain syntactic-rules, etc.). VOM 1.0 should parse most VHDL programs. However, it will not detect errors such as a wait statement in a process statement with an explicit sensitivity list. | |
| November 1st, 1994 |
| Verilog, XNF | |
| XNF to Verilog Translator | |
| ? | |
| translator(XNF->Verilog) | |
| M J Colley <martin@essex.ac.uk> | |
| ftp://ftp.caltech.edu/pub/dank/xnf2ver.tar.Z ? | |
|
This program was written by a postgraduate student as part
of his M.Sc course, it was designed to form part a larger
system operating with the Cadence Edge 2.1 framework. This
should be born in mind when considering the construction
and/or operation of the program.
[If anyone knows the current location of this program please let me know - ed (6/98)]. | |
| ? |
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