category: electrical engineering languages


Description:
These are languages used for simulating, designing, and specifying circuits.


Language:
VHDL
Package:
ALLIANCE
Version:
1.1
Parts:
compiler, simulator, tools and environment, documentation
Author:
?
Location:
ftp://ftp.ibp.fr/ibp/softs/masi/alliance/
Description:
ALLIANCE 1.1 is a complete set of CAD tools for teaching Digital CMOS VLSI Design in Universities. It includes VHDL compiler and simulator, logic synthesis tools, automatic place and route, etc... ALLIANCE is the result of a ten years effort at University Pierre et Marie Curie (PARIS VI, France).
Ports:
Sun4, also not well supported: Mips/Ultrix, 386/SystemV
Discussion:
alliance-request@masi.ibp.fr
Contact:
cao-vlsi@masi.ibp.fr
Updated:
Febuary 16th, 1993

Language:
EDIF (Electronic Design Interchange Format)
Package:
Berkeley EDIF200
Version:
7.6
Parts:
translator-building toolkit
Author:
Wendell C. Baker and Prof A. Richard Newton of the Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, CA
Location:
?? ftp://ic.berkeley.edu/pub/edif ??
Description:
?
Restriction:
no-profit w/o permission
Ports:
?
Updated:
1990/07

Language:
CASE-DSP (Computer Aided Software Eng. for Digital Signal Proc)
Package:
Ptolemy
Version:
0.6
Parts:
grahpical algorithm layout, code generator, simulator
Author:
?
Location:
ftp://ptolemy.eecs.berkeley.edu/pub/ptolemy/ptolemy0.6/
Description:
Ptolemy provides a highly flexible foundation for the specification, simulation, and rapid prototyping of systems. It is an object oriented framework within which diverse models of computation can co-exist and interact. For example, using Ptolemy a data-flow system can be easily connected to a hardware simulator which in turn may be connected to a discrete-event system, etc. Because of this, Ptolemy can be used to model entire systems.

In addition, Ptolemy now has code generation capabilities. from a flow graph description, Ptolemy can generate both C code and DSP assembly code for rapid prototyping. Note that code generation is not yet complete, and is included in the current release for demonstration purposes only.

Requires:
C++, C
Ports:
Sun-4, MIPS/Ultrix; DSP56001, DSP96002. FreeBSD
Status:
active research project
Discussion:
ptolemy-hackers-request@ohm.berkeley.edu
Contact:
ptolemy@ohm.berkeley.edu
Updated:
May 28th, 1996

Language:
SAOL, SASL (the MPEG-4 Structured Audio Orchestra Language and Structured Audio Score Language)
Package:
saolc
Version:
0.5
Parts:
parser, interpreter, grammar, core opcode implementation
Author:
Eric Scheirer, MIT Media Laboratory
Location:
http://sound.media.mit.edu/~eds/mpeg4
Description:
SAOL is an audio processing and digital synthesis and effects language. It is part of the MPEG-4 standard, and allows the flexible description of synthesizers and effects-processing algorithms within than toolset.

SAOL is historically related to Csound and other "Music N" languages, but is more flexible and easy to use than these. While maintaining features such as the instrument/score distinction and dual-rate processing, it adds user-defined opcodes, more well-defined rate semantics, more lexical flexibility, and an improved syntax.

References:
forthcoming
Conformance:
This implementation is being developed as the official Reference Software for the Structured Audio component of ISO 14496 (MPEG-4).
Features:
-
non-real time performance (unless your machine is much faster than my SGI Octane)
+
implements user-defined opcodes as macro expansion
+
standalone mode as well as bitstream processing
Bugs:
many known and being worked on.
Restrictions:
source code is released to the public domain
Requires:
C compiler only; lex/yacc to rebuild parser not much fun without audio capability
Ports:
At least SGI, Alpha, NT, Win95, Linux, and SunOS systems
Portability:
Word length and byte-order independent
Status:
Under active development
Discussion:
saol-dev-request@media.mit.edu to be added to the SAOL developers' mailing list
Help:
Eric Scheirer <eds@media.mit.edu>
Support:
Eric Scheirer <eds@media.mit.edu>
Announcements:
http://sound.media.mit.edu/~eds/mpeg4 and the mailing list
Contact:
Eric Scheirer <eds@media.mit.edu>
Updated:
07/1997

Language:
SPAM Compiler
Package:
SPAM
Version:
?
Parts:
?
Author:
?
Location:
http://www.ee.princeton.edu/spam
Description:
The SPAM Compiler is a retargetable optimizing compiler for embedded fixed- point DSP processors. SPAM is built on top of the SUIF Compiler, which serves as the "front and middle"-end. The back-end of the SPAM Compiler consists of two components. The first component is a set of data structures that store the various representations of the source program (e.g. calling graph, control-flow graphs, expression DAGs). The second component is a suite of retargetable algorithms that perform code generation and machine-dependent code optimization.
Updated:
?

Language:
Pascal, Lisp, APL, Scheme, SASL, CLU, Smalltalk, Prolog
Package:
Tim Budd's C++ implementation of Kamin's interpreters
Version:
?
Parts:
interpretors, documentation
Author:
Tim Budd <budd@cs.orst.edu>
Location:
? ftp://cs.orst.edu/pub/budd/kamin/*.shar
Description:
a set of interpretors written as subclasses based on "Programming Languages, An Interpreter-Based Approach", by Samuel Kamin.
Requires:
C++
Status:
?
Contact:
Tim Budd <budd@fog.cs.orst.edu>
Updated:
September 12th, 1991

Language:
VHDL
Package:
VHDL Object Model (VOM)
Version:
1.0
Parts:
parser
Author:
David Benz <dbenz@thor.ece.uc.edu> and Phillip Baraona <pbaraona@thor.ece.uc.edu>
Location:
ftp://thor.ece.uc.edu/pub/vhdl/tools/vhdl-object-model.tar.gz
Description:
VOM 1.0 is an object-oriented syntactic specification for VHDL written using the REFINE software design and synthesis environment. In simpler terms, it is a VHDL parser which builds an object tree from VHDL source code.

If you are interested in transforming VHDL into some other form (source code, whatever) you might be interested in this. The parse tree (in the form of an object tree) is provided, you would just need to add your own transformations.

VOM isn't complete. The semantic information is not included (type checking, certain syntactic-rules, etc.). VOM 1.0 should parse most VHDL programs. However, it will not detect errors such as a wait statement in a process statement with an explicit sensitivity list.

Updated:
November 1st, 1994

Language:
Verilog, XNF
Package:
XNF to Verilog Translator
Version:
?
Parts:
translator(XNF->Verilog)
Author:
M J Colley <martin@essex.ac.uk>
Location:
ftp://ftp.caltech.edu/pub/dank/xnf2ver.tar.Z ?
Description:
This program was written by a postgraduate student as part of his M.Sc course, it was designed to form part a larger system operating with the Cadence Edge 2.1 framework. This should be born in mind when considering the construction and/or operation of the program.

[If anyone knows the current location of this program please let me know - ed (6/98)].

Updated:
?

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