category: electrical engineering languages

`Description:`	These are languages used for simulating, designing, and specifying circuits.

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language/tool: CASE-DSP / Ptolemy

language/tool: SAOL / saolc

tool: SPAM

language/tool: VHDL / VHDL Object Model (VOM)

language/tool: Verilog / XNF to Verilog Translator

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The HTML is maintained by David Muir Sharnoff and the entries themselves are currently maintained by Bryan Miller.